This invention relates to clock signal distribution circuitry for integrated circuit devices of the type that are sometimes known as structured application-specific integrated circuits (“structured ASICs”).
Structured ASICs are devices that have some predetermined circuit characteristics, but that are also customizable to some degree. For example, a structured ASIC may include a two-dimensional array of many relatively small logic elements (referred to herein as hybrid logic elements or HLEs). The basic circuitry of these HLEs is always the same or substantially the same, and is provided by a subset of the masks that are used to make the structured ASIC. Accordingly, the masks in this subset can be always the same or substantially the same. The overall function(s) performed by an HLE can be customized to some extent by customizing one or more additional masks used to make a particular structured ASIC product. Similarly, connections to, from, and/or between HLEs can be customized by customizing additional masks used to make the product. Because the structured ASIC always has the same basic circuitry, the task of designing it to perform particular tasks is greatly simplified, speeded up, increased in reliability, and reduced in cost. An entire ASIC does not have to be designed “from scratch.” Instead, only the customizable masks have to be designed.
A possible use of structured ASIC technology is to produce ASICs that are functionally equivalent to programmed field-programmable gate arrays (“FPGAs”). After a logic design has been adequately “proven” in an FPGA, the design may be “migrated” to a structured ASIC. References such as Chua et al, U.S. patent application Ser. No. 10/884,460, filed Jul. 2, 2004, and Schleicher et al. U.S. patent application Ser. No. 11/037,633, filed Apr. 1, 2005, show this type of use of structured ASIC technology.
In structured ASICs of the type shown in the above-mentioned Chua et al. and Schleicher et al, references, the disposition (location or arrangement) of circuit functions (e.g., logic functions) on the structured ASIC can be quite different from the disposition of those functions on the FPGA that the structured ASIC is supposed to be functionally equivalent to. Accordingly, it may not be possible to simply duplicate on the structured ASIC the architecture of the circuitry that is provided on the related FPGA for routing or distributing clock signals to the functional circuitry. On the other hand, designing completely customized clock circuitry for each logic design that it may foe desired to implement using the structured ASIC is not thought to be a good approach for a number of reasons, such as the cost and complexity of the design task and the great importance of well-designed clock networks to optimal performance of the Structured ASIC.